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  1. agunos

    forcing top level signal in modelsim xe

    hello all. i have a hierarchichal vhdl design which one port is of the "inout std_logic_vector" type. This port connects to two internal components; one as an input and the other as an output. during simulation, i cannot force a value on this port(i am using the "force&quot...
    • agunos
    • Thread
    • Replies: 1
    • Forum: VHDL
  2. agunos

    clock multiplication

    Is it possible to multiply a clock signal up in frequency? For example, how could I get from a 1MHz reference to 10MHz?
    • agunos
    • Thread
    • Replies: 3
    • Forum: VHDL
  3. agunos

    rising and falling edge trigger

    Is it possible to trigger off both the rising and falling edge of the clock? I try doing this a nubmer of ways and when I go to synthesize, I get errors. All the examples I have seen only incorporate rising edge clock triggers. Thanks for any help. Hopefully I have given enough information.
    • agunos
    • Thread
    • Replies: 5
    • Forum: VHDL

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