Hi!
I have a component UDP, wrritten in VHDL, se below. Then I have a an entity that looks something like this:
entyity User_Logic is
port(
Bus2IP_BE :in std_logic_vector(0 to 3);
);
component UDP_IP is
port(
rx_dv :in std_logic;
)
end component;
Now I want to connect those two signals, but...
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