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  1. steadyeddie

    need help with synchronous input vs. clock

    srika, Thanks for the reply. I'll try your solution and see what happens.
  2. steadyeddie

    need help with synchronous input vs. clock

    Hi folks. I've been struggling with a problem with synchronous circuits in VHDL. Let's say that I have a clock feeding into two logic blocks that operate in parallel. The two blocks are mealey state machines. The first block generates output that is used as input for the second block. There...

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