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  1. DrummerD

    Basic Problem

    Thanks, but I'm not quite sure what you mean, or how this addresses what I'm trying to do.
  2. DrummerD

    Basic Problem

    Hi, I'm fairly new to VHDL, and have a question about a simple process. In order to make this easier to address, I've created a simplified version of the process. Essentially, I have an entity with one input (std_logic_vector) and one ouput, (std_logic). All I want to do is to have my output...

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