Hello,
i'm new in VHDL and in simulation with ModelSim and it is the first time that i post something to a forum.
I have a problem to simulate in ModelSim InOut Ports:
For example:
process(clk1)
begin
if clk1'event and clk1='1' then
if wrreq='1' then temp<=R;
elsif rdreq='1' then...
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