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Hi all, I am writing a testbench and I need to know something about file IO. How can you read a byte from a file and convert it to a std_logic_vector(7 downto 0)? I have looked at all the text IO stuff, but none of it fits my need. What I want is to read a pixel from a bitmap file, and...

Hi all, I need some help with this. I have an entity that looks like this entity test is port( clk, rst, valid, go: in std_logic; din: in std_logic_vector(25 downto 0); dinLen: in std_logic_vector(4 downto 0); dout: out std_logic_vector(7 downto 0); rdy, end: out std_logic); end...

Did that. Fixed the problem. Thanks guys

My full code is below library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity findCategory is port( clk, rst, validIn, eobIn: in std_logic; zrl: in std_logic_vector(5 downto 0); value: in std_logic_vector(10 downto 0); eobOut, validOut: out std_logic; index: out...

Hi, When I try to synthesise a vhdl module, I get the following warnings. WARNING:Xst:646 - Signal <catcheckval4> is assigned but never used. I understand that this can happen if I assign values to a signal, but is never used as an assignment to other signals. The thing is, this happens on...

I fixed the problem in my second posting. It was because I was accessing a project on a networked PC that was accessed by another user. The first warning in my first post is also occurring in files that previously worked in a post-translate simulation.

Also, I am having a problem with the waveform viewer in ModelSim. When I try to add signals to the waveform viewer, some of them cause the ModelSim application to close down completely, with no error or warning. Others cause the following warnings [code]# ** Warning: (vsim-WLF-5000) Log file...

Hi guys, when I try to do a post-translate simulation of some code of mine, i get the following error [code]# WARNING[1]: zerorunlength_translate.vhd(3730): No default binding for component: &quot;x_lut2&quot;. (No entity named &quot;x_lut2&quot; was found)[\code] Any idea what the problem...