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  • Users: morem
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  1. morem

    Clock duty cycle

    Hi, I am looking for a way to change the duty cycle of the clock. The global clock is received from outside, and I need the new clock with the same frequency but let's say 75% duty cycle. The problem is that the design should be synthesized (can't use after stat.) Thanks.
    • morem
    • Thread
    • Replies: 2
    • Forum: VHDL

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