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  1. Howard123

    VHDL code, what's wrong

    Thanks jmxntg, It sounds like the code is OK, it's just the way it's simulated on Max Plus. I have tried Quartus II and the code simulates OK. Thanks again. Howard
  2. Howard123

    VHDL code, what's wrong

    Hello, The following code comes from the Altera web site. It indicates the implementation is incorrect. It seems to simulate OK. Can anyone tell me what's wrong with it? ENTITY dff IS PORT( enable : IN BIT; d, clk : IN BIT; q : OUT BIT ); END dff...

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