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how to make division synthesizable in a case statement?? pls help
i have two 8 bit std_logic_vector inputs and one 16 bit std_logic_vector output eg. aluout <= data/accum; this statement is within a case statement and i know that it is not syntesizable and i met with an error called operator arugement mismatch.. so i tried using a function call to just...- vampirebat83
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- Forum: VHDL
