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Synthesis of constants
Hello, Some synthesis tools do support constants. Basically it is setting it either to a VCC or a GND. I have resolved my issue because I used to be using the constants to convert from std_logic_vector to ints and vice versa, but I started using behavioural code which eliminated the need for... -
loops in vhdl
Hi anjaxe1, Looping is supported in VHDL. Xilinx is a vendor of programmable logic devices, and so they don't really "support" looping, it is VHDL that does that. As for your issues, what kind of problems are you having?? Beemer -
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Synthesis of constants
Hello all, I am trying to synthesize constant values. Previously, I had them as signals, where the logic produced actually fit my device (760 out of 784 total CLBs). As soon as I modified the signals to constants, the logic jumped to 1068 CLBs, and I could not fit onto the device anymore...
