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Problem with simalution : TImer code
Hi ! I have a problem when I'm simulating this code ! The process run right but when I'll copy the vector on the output my value are changing with X state but it should be 1 use IEEE.Std_Logic_1164.all; use IEEE.numeric_std.all; entity time_set is port(selected, run, minup, mindown...- clementval
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- Forum: VHDL
