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  1. tecton

    i can't activate a signal after 12 cycles. pls help

    hi everybody, i'm new in vhdl and i'm trying to activate a signal after 12 cycles and then di-activate it again. for example, start-0-0-0-0-0-0-0-0-0-0-0-0-1-0-end i have these errors in Modelsim, error: No feasible emtries for infix operator "+". error: Type error resolving infix expression...
    • tecton
    • Thread
    • Replies: 1
    • Forum: VHDL

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