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Signal xx cannot be synthesized, bad synchronous description
I have written a 4-bit ALU with CCR in VHDL, but when I try to obtain the Synthesis Report in Xilinx ISE 9.2i I get this error: line 39: Signal C cannot be synthesized, bad synchronous description. Line 39 is: " PROCESS(s, CLK) IS" library IEEE; use IEEE.STD_LOGIC_1164.ALL; use...
