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clk divider not working as expected
i was playing around with the my code above but originally the line that reads: variable cnt: integer range 0 to 2 :=0; initially read : variable cnt: integer range 0 to 4 :=0; sorry for the confusion- andychess86
- Post #2
- Forum: VHDL
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clk divider not working as expected
thread284-1502031 Hi, using the advice given by the user of the alias: jeandelfrigo, I wrote code to divide a 125 MHz clock into a 5 MHz. I use a counter that counts from 0 to 4 and when the counter is equal to 0,1, or 2 I let the clk be a '1'. otherwise I let clk be a '0'. However when I look...- andychess86
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- Replies: 2
- Forum: VHDL
