Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Search results for query: *

  1. elin05

    Warning: Signal <> is assigned but never used.

    I'm new to VHDL and could use some help. I'm getting the "Warning: Signal <reset_default> is assigned but never used." Can I fix this without adding another port to my entity? Thanks Eric Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use...
    • elin05
    • Thread
    • Replies: 0
    • Forum: VHDL

Part and Inventory Search

Back
Top