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Transport delay in vhdl need help
I have problems using the transport statement in vhdl. This is what i have: Pulse <= not SOC and MD; ckl <= transport pulse after 20us; for some reason my ckl signal is just my pulse signal. no matter what i adjust the delay to, ckl just replicates pulse. Is there something else I need to...- wuzzaap123
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- Forum: VHDL
