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Unsupported Clock statement
Thanks for your answer. I try to synthesize DDR SDRAM Controller but it's not going very easy. Unfortunately I could not separate my state automaton to several processes:( But I would try to find a way around.- annadorian
- Post #3
- Forum: VHDL
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Unsupported Clock statement
Hi all, I have a problem and I can not find a solution:( So I have a code which I could simulate without any problems but I can not sintethize it with Xilinx Project Navigator! I realized a state automaton and it has to work on both edges of signals but in Xilinx I have error "Unsupported Clock...- annadorian
- Thread
- Replies: 3
- Forum: VHDL
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Synthesis of "wait until" with Xilinx Project Navigator
Hi all! I have a test bench for one of my designs and it works perfectly but currently I have to test my design with a real FPGA. So I have to synthesize it using Xilinx Project Navigator. Here I have some problems:( I can not synthesize fragment which is listed below and I do not know how to...- annadorian
- Thread
- Replies: 1
- Forum: VHDL
