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  1. PouriaPouria

    VHDL state machine timing problems

    Hi there. I'm trying to design a state machine to Run at 100 MHz in an Actel FPGA. Most of my states have 6 or more exits. My questions is how many exits can I have on one single state so that the Logic that is generated by the syntisizer dose not have a delay more then 10ns (100MHz clock)...

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