Hi all,

I'm using ghdl to compile some vhdl code and I can't get the "and" and "or" operators to work. Here's the file where I'm using it:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity question3 is
Port (D :in std_logic_vector(3 downto 0);
Y :out std_logic_vector(3 downto 0));
end entity question3;

architecture dataflow of question3 is
signal row0, row2, row3, row8, row9, rowD, rowE : std_logic_vector(3 downto 0) := "0000";

begin
row0 <= (not D(3)) and (not D(2)) and (not D(1)) and (not D(0));
row2 <= (not D(3)) and (not D(2)) and D(1) and (not D(0));
row3 <= (not D(3)) and (not D(2)) and D(1) and D(0);
row8 <= D(3) and (not D(2)) and (not D(1)) and (not D(0));
row9 <= D(3) and (not D(2)) and (not D(1)) and D(0);
rowD <= D(3) and D(2) and (not D(1)) and D(0);
rowE <= D(3) and D(2) and D(1) and (not D(0));

Y(3) <= '0' or row8 or rowD or row3;
Y(2) <= row2 or row9 or row3 or rowD;
Y(1) <= row9 or row2 or row0 or rowE;
Y(0) <= '0' or row0 or row8 or rowE;
end architecture dataflow;

I get an error invoked on each line that uses "and" or "or" that says:
no function declarations for operator "and"/"or"

I tried passing in "--ieee=synopsys" as my library and including "ieee.std_logic_unsigned" but to no avail.

You making the wrong use of "and" and "or" and confuse the use of vectors and bits.

For row0 that is a vector u must use "&" like (not D(3) & not D(2) ) and so on.

For your output you use vectors where there should be bits.

Y(3) <= '0' or row8(somebit) or rowD(somebit) or row3(somebit);


Do you understand me?