I'm trying to implement a square root carry select adder (SQCSA) in Verilog. It's a chain of carry select adders (CSA's) with variable width blocks. The least significant block is a 2 bit CSA, the next 3 bit and so on. For example to build a 9-bit SQSCA, you would have three CSA's - 2,3 and 4 bits wide. The first one would compute bits a0,a1, the second a2,a3,a4 and the third a5,a6,a7,a8  
My problem is passing the input bits to the appropriate adder.  For a linear 2 bit CSA I did a generate statement with a for loop  passing the inputs like this a[2*i+1:2*i] on each increment of i. But because the blocks for the SQCSA all have different width I can't really do anything like that.

Any help would be greatly appreciated.
Thank you.